Semiconductor packages equipped with wireless data and communication systems incorporate various RF (radio frequency) transmitting structures, which sometimes are built on-chip or in-package. RF signals are generally considered to have a frequency falling in approximately the 3 kHz to 300 GHz range, with frequencies in the domain between about 300 MHz (0.3 GHz) and 300 GHz typically being referred to as microwaves. Electromagnetic RF waves or signals are conveyed through the semiconductor packages or devices by conductive structures referred to as “transmission lines.” Transmission lines, as an example, are used for interconnecting individual electrical elements together in a Monolithic Microwave Integrated Circuit (MMIC), and for interconnecting MMICs together within microwave MultiChip Modules (MCMs).
In general, a microwave transmission line structure generally includes at least two electric conductors or lines wherein one of the lines forms a ground (also referred to as “ground plane”) and the other forms a signal transmission line. The signal transmission line is variously arranged and combined with one or more ground planes or ground lines to form different types of conductive transmission line structures such as microstrips, striplines, and waveguides to serve various RF signal applications. The transmission lines and ground conductors or planes are generally supported by some type of insulating substrate or material such as a dielectric.
As semiconductor technology continues to advance and chip package size shrinks, such as by employing 3D die stacking, the distance between metal layers in the conductive CMOS (complementary metal-oxide semiconductor) structure becomes smaller resulting in increasingly larger capacitance between the metal layers which compromises performance of RF devices. In addition, designing and fabricating transmission line structures on-chip in a single chip or die becomes increasingly difficult with shrinking die packages in advanced semiconductor manufacturing technology nodes like the 20 nm process.
All drawings are schematic and are not drawn to scale.